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Espressif Systems /ESP32-P4 /DMA /COMMONREG_INTSIGNAL_ENABLE0

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Interpret as COMMONREG_INTSIGNAL_ENABLE0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL)ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL 0 (ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL)ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL 0 (ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL)ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL 0 (ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL)ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL 0 (ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL)ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL 0 (ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL)ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL 0 (ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL 0 (ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL 0 (ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL 0 (ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL 0 (ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL 0 (ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL)ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL 0 (ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL)ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL

Description

NA

Fields

ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL

NA
ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL

NA
ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL

NA
ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL

NA
ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL

NA
ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL

NA
ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL

NA
ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL

NA
ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL

NA
ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL

NA
ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL

NA
ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL

NA
ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL

NA

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data